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1 features applications description SN75LVCP422 www.ti.com ................................................................................................................................................................................................... slls972 ? march 2009 two channel sata 3-gbps redriver excellent jitter and loss compensation capability to over 20 inch fr4 trace data rates up to 3 gbps high protection against esd transient sata gen 2.6, esata compliant ? hbm: 8000v sata hot-plug capable ? cdm: 1500v supports common-mode biasing for oob signaling with fast turn-on ? mm: 200v channel selectable pre-emphasis 20-pin ssop package fixed receiver equalization pin compatible with pi2eqx3211a and pi2eqx3211b integrated termination low power ? < 200 mw typ notebooks, desktops, docking stations, ? < 5 mw in sleep mode servers, and workstations ? 15% typ lower power in auto low power mode the SN75LVCP422 is a dual channel, single lane sata redriver and signal conditioner supporting data rates up to 3 gbps. the device complies with sata specification revision 2.6 and esata requirements. the SN75LVCP422 operates from a single 3.3-v supply. integrated 100- ? line termination and self-biasing make the device suitable for ac coupling. the inputs incorporate an oob detector, which automatically turns the differential outputs off while maintaining a stable output common-mode voltage compliant to sata link. the device is also designed to handle ssc transmission per sata spec. the SN75LVCP422 handles interconnect losses at both its input and output. the built-in transmitter pre-emphasis feature is capable of applying 0 db or 2.5 db of relative amplification at higher frequencies to counter the expected interconnect loss. on the receive side the device applies a fixed equalization of 7 db to boost input frequencies near 1.5 ghz. collectively, the input equalization and output pre-emphasis features of the device work to fully restore sata signal integrity over extended cable and backplane pathways. the device is hot-plug capable (1) preventing device damage under device hot-insertion such as async signal plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal. (1) requires use of ac coupling capacitors at differential inputs and outputs. ordering information (1) part number part marking package SN75LVCP422db lvcp422 20-pin ssop tube SN75LVCP422dbr lvcp422 20-pin ssop reel (large) (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
typical application SN75LVCP422 slls972 ? march 2009 ................................................................................................................................................................................................... www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 2 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): SN75LVCP422 ich r hdd sata cable (2m) esata connector pc motherboard r = SN75LVCP422 ich r notebook dock dock connector in notebook and desktop motherboard in notebook dock hdd sata cable (2m) esata connector r = SN75LVCP422
SN75LVCP422 www.ti.com ................................................................................................................................................................................................... slls972 ? march 2009 figure 1. data flow block diagram table 1. control logic en d0 d1 function 0 x x low power mode 1 0 0 normal sata output (default state); ch 0 and ch 1 0 db 1 1 0 ch 0 2.5 db pre-emphasis; ch 1 0 db 1 0 1 ch 1 2.5 db pre-emphasis; ch 0 0 db 1 1 1 ch 0 and ch 1 2.5 db pre-emphasis copyright ? 2009, texas instruments incorporated submit documentation feedback 3 product folder link(s): SN75LVCP422 ctrl rtrt rtrt en [20] gnd [5, 9, 12, 16] v = 1.6 v typ bb rx_0p [3] rx_0n [4] tx_op [18] tx_on [17] equalizer driver oob detect v bb rx_1n [13] rx_1p [14] SN75LVCP422 equalizer driver oob detect tx_1n [8] tx_1p [7] d1 [10] d0 [1] v [2, 6, 15, 19] cc
pin assignment SN75LVCP422 slls972 ? march 2009 ................................................................................................................................................................................................... www.ti.com db package top view terminal functions pin name description pin name description 1 d0 (1) pre-emphasis _0 11 nc no connect 2 vcc power 12 gnd ground 3 rx_0p input 0, non-inverting 13 rx_1n input 1, non-inverting 4 rx_0n input 0, inverting 14 rx_1p input 1, inverting 5 gnd ground 15 vcc power 6 vcc power 16 gnd ground 7 tx_1p output 1, inverting 17 tx_0n output 0, inverting 8 tx_1n output 1, non-inverting 18 tx_0p output 0, non-inverting 9 gnd ground 19 vcc power 10 d1 (1) pre-emphasis_1 20 en (2) enable (1) d0 and d1 are tied to vcc via an internal pu resistor. (2) en tied to vcc via an internal pu resistor. 4 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): SN75LVCP422 en vcc tx_0p tx_0n gnd vcc rx_1p rx_1n gnd nc d0 vcc rx_0p rx_0n gnd vcc tx_1p tx_1n gnd d1 1 23 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SN75LVCP422db
typical device implementation detailed description input equalization output pre-emphasis low power mode SN75LVCP422 www.ti.com ................................................................................................................................................................................................... slls972 ? march 2009 each differential input of the SN75LVCP422 has 7 db of fixed equalization in its front stage. the equalization amplifies high frequency signals to correct for loss from the transmission channel. the input equalizer is designed to recover signal even when no eye is present at the receiver and affectively supports fr4 trace at the input anywhere from < 4 inches to 20 inches or < 10 cm to > 50 cm. the SN75LVCP422 provides single step pre-emphasis from 0 db to 2.5 db at each of its differential outputs. pre-emphasis is controlled independently for each channel and is set by the control pins d0 and d1 as shown in table 1 . the pre-emphasis duration is 0.5 ui or 133 ps (typ) at sata 3-gbps speed. two low power modes are supported by the SN75LVCP422: sleep mode (triggered by en pin, en = 0 v) ? low power mode is controlled by the enable (en) pin. in its default state this pin is internally pulled high. pulling this pin low puts the device in sleep mode within 2 us (max). in this mode all active components of the device are driven to their quiescent level and differential outputs are driven to hi-z (open). maximum power dissipation in this mode is 5 mw. exiting from this mode to normal operation requires a maximum latency of 20 m s. auto low power mode (triggered when a given channel is in electrical idle state, en = v cc ) copyright ? 2009, texas instruments incorporated submit documentation feedback 5 product folder link(s): SN75LVCP422 3.3v esata connector gpio 1.0uf 0.1uf sata host 10nf 10nf 10nf 10nf 10nf 10nf 10nf 10nf 0.01uf note: 1) place supply caps close to device pin 2) en can be left open or tied to supply when no external contro l is implem ented 3) output pre-emphasis (d1, d0) is shown enabled . setting wi ll depend on device placem ent relative to esata connector en vcc tx_0p tx_0n gnd vcc rx_1p rx_1n gnd nc d0 vcc rx_0p rx_0n gnd vcc tx_1p tx_1n gnd d1 1 10 20 11 SN75LVCP422db
out-of-band (oob) support device power absolute maximum ratings dissipation ratings SN75LVCP422 slls972 ? march 2009 ................................................................................................................................................................................................... www.ti.com ? the device enters and exits low power mode by actively monitoring the input signal (v idp-p ) level on each of its channels independently. when the input signal on either or both channels is in the electrical idle state, i.e. v idp-p < 50 mv, and stays in this state for > 3 m s, the associated channel(s) enters the low power state. in this state, the output of the associated channel(s) is driven to v cm , and the device selectively shuts off some circuitry to lower power by up to 20% of its normal operating power. exit time from auto low power mode is less than 50 ns. ? as an example, if under normal operating conditions the device is consuming typical power of 200 mw, when the device enters this mode, i.e. the condition for auto-low power mode is met, power consumption can drop down to 160 mw. the device enters normal operation within 50 ns of signal activity detection. the squelch detector circuit within the device enables full detection of oob signaling as specified in sata specification 2.6. differential signal amplitude at the receiver input of 50 mv p-p or less is not detected as an activity and hence is not passed to the output. differential signal amplitude of 150 mv p-p or more is detected as an activity and therefore passed to the output indicating activity. squelch circuit on/off time is 5 ns maximum. while in squelch mode outputs are held to v cm . the sn75lvcl412 is designed to operate from a single 3.3-v supply. always practice proper power supply sequencing procedures. apply v cc first before any input signals are applied to the device. the power down sequence is in reverse order. over operating free-air temperature range (unless otherwise noted) (1) value unit supply voltage range (2) v cc ? 0.5 to 6 v voltage range differential i/o ? 0.5 to 4 v control i/o ? 0.5 to v cc + 0.5 v electrostatic discharge human body model (3) 8000 v charged-device model (4) 1500 v machine model (5) 200 v continuous power dissipation see dissipation rating table (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential voltages, are with respect to network ground terminal. (3) tested in accordance with jedec standard 22, test method a114-b. (4) tested in accordance with jedec standard 22, test method c101-a. (5) tested in accordance with jedec standard 22, test method a115-a. pcb jedec derating factor (1) t a = 85 c package t a 25 c standard above t a = 25 c power rating 20-pin ssop (db) low-k 952 mw 9.52 mw/ c 381 mw high-k 1149 mw 11.49 mw/ c 460 mw (1) this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 6 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): SN75LVCP422
thermal characteristics recommended operating conditions electrical characteristics SN75LVCP422 www.ti.com ................................................................................................................................................................................................... slls972 ? march 2009 over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max (1) unit r q jb junction-to-board thermal resistance 58 c/w r q jc junction-to-case thermal resistance 65 c/w p d device power dissipation d0, d1, en = 3.3 v, k28.5 pattern at 3 gbps, 300 mw v id = 700 mv p-p , v cc = 3.6 v p sd device power dissipation, under low en = 0 v, k28.5 pattern at 3 gbps, v id = 700 5 mw power mv p-p , v cc = 3.6 v (1) the maximum rating is simulated under 3.6-v v cc . with typical values measured at v cc = 3.3 v, t a = 25 c; all temperature limits are assured by design parameter conditions min typ max units v cc supply voltage 3 3.3 3.6 v c coupling coupling capacitor 12 nf t a operating free-air temperature 0 85 c over recommended operating conditions (unless otherwise noted) parameter conditions min typ max units device parameters i cc supply current, active mode en, d0, d1 in default state, k28.5 pattern at 3 gbps, 55 77 ma v id = 700 mv p-p , v cc = 3.3 v i ccsdwn shutdown current en = 0 v 1 ma i cc-lp supply current in auto low low power mode activated 50 ma power mode maximum data rate 3.0 gbps t pdelay propagation delay measured using k28.5 pattern, see figure 4 300 500 ps t enb device enable time enb = l h 20 m s t dis device disable time enb = h l 2 m s autolp entry auto low power entry time electrical idle at input, see figure 7 6 m s autolp exit auto low power exit time after first signal activity, see figure 7 45 ns v oob input oob threshold see figure 5 50 100 150 mv p-p t oob1 oob mode enter see figure 5 5 ns t oob2 oob mode exit see figure 5 5 ns control logic v ih high-level input voltage 1.4 v v il low-level input voltage 0.5 v v inhys input hysteresis 100 mv i ih high-level input current 10 m a i il low-level input current 10 m a receiver ac/dc z diffrx differential input impedance 85 100 115 ? z serx single-ended input impedance 40 ? vcm rx common-mode voltage 1.6 v copyright ? 2009, texas instruments incorporated submit documentation feedback 7 product folder link(s): SN75LVCP422
SN75LVCP422 slls972 ? march 2009 ................................................................................................................................................................................................... www.ti.com electrical characteristics (continued) over recommended operating conditions (unless otherwise noted) parameter conditions min typ max units rl diffrx differential mode return loss f = 150 mhz ? 300 mhz 18 db f = 300 mhz ? 600 mhz 14 f = 600 mhz ? 1.2 ghz 10 f = 1.2 ghz ? 2.4 ghz 8 f = 2.4 ghz ? 3.0 ghz 3 rl cmrx common-mode return loss f = 150 mhz ? 300 mhz 5 db f = 300 mhz ? 600 mhz 5 f = 600 mhz ? 1.2 ghz 2 f = 1.2 ghz ? 2.4 ghz 1 f = 2.4 ghz ? 3.0 ghz 1 v diffrx differential input voltage pp f = 150 mhz ? 300 mhz 200 2000 mv/ppd ib rx impedance balance f = 150 mhz ? 300 mhz 30 db f = 300 mhz ? 600 mhz 30 f = 600 mhz ? 1.2 ghz 20 f = 1.2 ghz ? 2.4 ghz 10 f = 2.4 ghz ? 3.0 ghz 4 t 20-80rx rise/fall time rise times and fall times measured between 20% and 67 136 ps 80% of the signal t skewrx differential skew difference between the single-ended mid-point of the 50 ps rx+ signal rising/falling edge and the single-ended mid-point of the rx ? signal falling/rising edge transmitter ac/dc z difftx pair differential impedance 85 115 ? z setx single-ended input impedance 40 ? rl difftx differential mode return loss f = 150 mhz ? 300 mhz 14 db f = 300 mhz ? 600 mhz 8 f = 600 mhz ? 1.2 ghz 6 f = 1.2 ghz ? 2.4 ghz 6 f = 2.4 ghz ? 3.0 ghz 3 rl cmtx common-mode return loss f = 150 mhz ? 300 mhz 5 db f = 300 mhz ? 600 mhz 5 f = 600 mhz ? 1.2 ghz 2 f = 1.2 ghz ? 2.4 ghz 1 f = 2.4 ghz ? 3.0 ghz 1 ib tx impedance balance f = 150 mhz ? 300 mhz 30 db f = 300 mhz ? 600 mhz 20 f = 600 mhz ? 1.2 ghz 10 f = 1.2 ghz ? 2.4 ghz 10 f = 2.4 ghz ? 3.0 ghz 4 diff vpptx differential output voltage pp f = 1.5 ghz, d0/d1 = 0, refer to figure 2 for test 400 585 700 mvpp setup diff vpptx_pe differential output voltage pp f = 1.5 ghz, d0/d1 = 1, refer to figure 2 for test 600 790 965 mvpp setup output pre-emphasis at 1.5 ghz (when enabled) 2.5 db v cmtx common-mode voltage 1.97 v v cmtx_ac ac cm voltage maximum amount of ac cm signal at tx 20 50 mvpp t 20-80tx rise/fall time rise times and fall times measured between 20% and 67 83 136 ps 80% of the signal, d1/d0 = 0 v 8 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): SN75LVCP422
SN75LVCP422 www.ti.com ................................................................................................................................................................................................... slls972 ? march 2009 electrical characteristics (continued) over recommended operating conditions (unless otherwise noted) parameter conditions min typ max units t skewtx differential skew difference between the single-ended mid-point of the 7 20 ps tx+ signal rising/falling edge and the single-ended mid-point of the tx ? signal falling/rising edge jitter (with pre-emphasis disabled; measured at device pin + 2 " loadboard trace) tj tx total jitter (1) ui = 333 ps, +k28.5 control character; d1/d0 = 0 v 30 67 ps-pp dj tx deterministic jitter (1) ui = 333 ps, +k28.5 control character; d1/d0 = 0 v 10 33 ps-pp rj tx random jitter (1) ui = 333 ps, +k28.7 control character; d1/d0 = 0 v 1.7 2.0 ps-rms jitter (with pre-emphasis enabled; measured as shown in figure 2 ) tj tx total jitter (1) ui = 333 ps, +k28.5 control character; d1/d0 = vcc 60 100 ps-pp dj tx deterministic jitter (1) ui = 333 ps, +k28.5 control character; d1/d0 = vcc 33 67 ps-pp rj tx random jitter (1) ui = 333 ps, +k28.7 control character; d1/d0 = vcc 1.7 2.0 ps-rms (1) t j = (14.1 rj sd + dj) where rj sd is one standard deviation value of rj gaussian distribution. t j measurement is at the sata connector and includes jitter generated at the package connection on the printed circuit board and at the board interconnect. figure 2. output jitter measurement test setup copyright ? 2009, texas instruments incorporated submit documentation feedback 9 product folder link(s): SN75LVCP422 10" fr4 lvcp422 ji tter measurement point 6" fr4 jitter measurement setup *signal source *signal source jitter measurement point *source ji tte r mea sure me nts (ps) total jitt er 32pp determinis tic jitt er 8pp random jit ter 1.7rms
SN75LVCP422 slls972 ? march 2009 ................................................................................................................................................................................................... www.ti.com figure 3. 10 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): SN75LVCP422 pc mb esata connector c b a sata host redriver redriver on pc motherboard note*: trace lengths are suggested values based on ti lab measureme nts (taken with output pre-emphasis enabled on both channels) to meet sata l oss and jitter spec. actual trace length supported by lvcp422 may be more or less t han suggested values and will depend on board layout, number of connectors used in the sata signal path, and sata host and esata connector design. suggested trace length using lvcp422 in pc mb and pc dock pc mb esata connector sata host redriver dock b1 b2 c a redriver on dock board pc mb typ* (inch) max* (inch) b 4 to 16 18 c 2 to 4 6 a 6 to 20 24 suggested trace lengths dock typ* (inch) max* (inch) b = (b1+b2) 8 to 14 16 c 2 to 4 6 a 10 to 18 22 suggested trace lengths
SN75LVCP422 www.ti.com ................................................................................................................................................................................................... slls972 ? march 2009 figure 4. propagation delay timing diagram figure 5. oob enter and exit timing figure 6. tx differential output with 2.5 db pre-emphasis step copyright ? 2009, texas instruments incorporated submit documentation feedback 11 product folder link(s): SN75LVCP422 t pdelay t pdelay in out 50 mv in+vcm in- out+ vcm out- t oob2 t oob1 0db 2.5 db vcm 0db 1-bit 1 to n bits 1-bit 1 to n bits t de t de 2.5 db diff tx vpp diff tx_pe vpp
SN75LVCP422 slls972 ? march 2009 ................................................................................................................................................................................................... www.ti.com figure 7. auto low power mode timing 12 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): SN75LVCP422 t oob1 vcm rx vcm t x autolp ent ry autolp exit rx_0,1p rx_0,1n tx_0,1p tx_0,1n power saving mode
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN75LVCP422db active ssop db 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim SN75LVCP422dbr active ssop db 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 16-mar-2009 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN75LVCP422dbr ssop db 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN75LVCP422dbr ssop db 20 2000 367.0 367.0 38.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2
mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
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